外文翻译The function introduction of AT89S52.doc

1、附录外文资料英文部分：The function introduction of AT89S52Features(R) * Compatible with MCS-51 Products* 8K Bytes of In-System Programmable (ISP) Flash Memory Endurance: 1000 Write/Erase Cycles* 4.0V to 5.5V Operating Range* Fully Static Operation: 0 Hz to 33 MHz* Three-level Program Memory Lock* 256 x 8-bit I

2、nternal RAM* 32 Programmable I/O Lines* Three 16-bit Timer/Counters* Eight Interrupt Sources* Full Duplex UART Serial Channel* Low-power Idle and Power-down Modes* Interrupt Recovery from Power-down Mode* Watchdog Timer* Dual Data Pointer* Power-off FlagDescription：The AT89S52 is a low-power, high-p

3、erformance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pin-out .The on-chip Flash allows the program memory t

4、o be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded con

5、trol applications.The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry

6、. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode sa

7、ves the RAM con-tents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.Pin Description：VCC：Supply voltage.GND：Ground.Port 0：Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s ar

8、e written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash progra

9、mming and outputs the code bytes during program verification. External pull-ups are required during program verification.Port 1：Port 1 is an 8-bit bidirectional I/O port with internal pull-ups . The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are p

10、ulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source because of the internal pull-ups. current (I IL) In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/

11、counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table . Port 1 also receives the low-order address bytes during Flash programming and verification.Port Pin Alternate FunctionsP1.0 T2 (external count input to Timer/Counter 2), clock-outP1.1 T2EX (Timer/Counter 2 capture/r

12、eload trigger and direction control)P1.5 MOSI (used for In-System Programming)P1.6 MISO (used for In-System Programming)P1.7 SCK (used for In-System Programming)Port 2：Port 2 is an 8-bit bidirectional I/O port with internal pull-ups . The Port 2 output buffers can sink/source four TTL inputs .When 1

13、s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs ,Port 2 pins that are externally being pulled low will source because of the internal pull-ups .current (I IL) Port 2 emits the high-order address byte during fetches from external progra

14、m memory and during accesses to external data memory that use 16-bit addresses (MOVX DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data-memory that use 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Reg

15、ister .Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3：Port 3 is an 8-bit bidirectional I/O port with internal pull-ups .The Port 3 output buffers can sink/source four TTL inputs .When 1s are written to Port 3 pins, they are

16、pulled high by the internal pull-ups and can be used as inputs. As inputs , Port 3 pins that are externally being pulled low will source because of the pull-ups .current (I IL) Port 3 also serves the functions of various special features of the AT89S52, as shown in the following table .Port 3 also r

17、eceives some control signals for Flash programming and verification.Port Pin Alternate FunctionsP3.0 RXD (serial input port)P3.1 TXD (serial output port)P3.2 INT0 (external interrupt 0)P3.3 INT1 (external interrupt 1)P3.4 T0 (timer 0 external input)P3.5 T1 (timer 1 external input)P3.6 WR (external d

18、ata memory write strobe)P3.7 RD (external data memory read strobe)RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives high for 96 oscillator periods after the Watchdog times out .The DISRTO bit in SFR AUXR (address 8EH) can be

19、 used to disable this feature. In the default state of bit DISRTO , the RESET HIGH out feature is enabled.ALE/PROG：Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external-memory. This pin is also the program pulse input (PROG) during Flash p

20、rogramming. In normal operation, ALE is emitted at a constant rate of1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bi

21、t 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEN：Program Store Enable (PSEN) is the read strobe to external pr

22、ogram memory. When the AT89S52 is executing code from external pro- gram memory, PSEN is activated twice each machine activations are skipped during cycle, except that two PSEN each access to external data memory.EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device

23、 to fetch code from external pro-gram memory locations starting at 0000H up to FFFFH. EA will beNote, however, that if lock bit 1 is programmed, internally latched on reset. EA should be strapped to V CC for internal program executions .This pin also receives the 12-volt programming enable volt-age

24、(V PP) during Flash programming.XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2：Output from the inverting oscillator amplifier.Special Function Registers：A map of the on-chip memory area called the Special Function Register (SFR) space is sho

25、wn in Table 1.Table 1 . AT89S52 SFR Map and Reset ValuesNote that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip .Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User softwa

26、re should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (

27、shown in Table 3) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt s

28、ources in the IP register.Table 2 . SymbolFunctionTF2Timer 2 overflow flag set by a Timer 2overflow and must be cleared by software. TF2 will not be set when either RCLK = 1 or TCLK = 1.EXF2Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2

29、 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).RCLKReceive clock enable. When set, causes the serial port to use Timer 2 overflow pu

30、lses for its receive clock in serial port Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.TCLKTransmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows

31、 to be used for the transmit clock.EXEN2Timer2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.TR2Start/Stop control for Timer 2. TR2 =

32、 1 starts the timer.C/T2Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge triggered).CP/RL2Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0 causes automatic reloads to

33、 occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 1

34、6-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1.The user should always initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register.Table 3 a. AUX

35、R: Auxiliary Register：Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to “1” during power up. It can be set and rest under software control and is not affected by reset.Table 3 b. AUXR1: Auxiliary Register 1：Memory Organization：MCS-51 devices have a

36、separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.Program Memory：If the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S52, if EA is connected to VCC , program fetches to addresse

37、s 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory.Data Memory：The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128

38、bytes have the same addresses as the SFR space but are physically separate from SFR space. Data Memory The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses a

39、s the SFR space but are physically separate from SFR space.For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2).MOV 0A0H, #dataInstructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressi

40、ng instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).MOV R0, #dataNote that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are avail-able as stack space.Watchdog Timer： (One-time Enabled with

41、Reset-out) The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 13-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H

42、in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset

43、or WDT over- flow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin.Using the WDT：To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1

44、H to WDTRST to avoid a WDT over-flow. The 13-bit counter overflows when it reaches 8191(1FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 8191 machine cycles. T

45、o reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 96xTOSC, where TOSC=1/FOSC. To make the best use of the WDT,

46、 it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.WDT During Power-down and Idle：In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the

47、WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S52 is reset.

48、Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode. To ensure that the WDT does not overflow within a fe